US 12,334,151 B2
Non-volatile memory stored with encoded data
Win-San Khwa, Hsinchu (TW); Jui Jen Wu, Hsinchu (TW); Jen-Chieh Liu, Hsinchu (TW); and Meng-Fan Chang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jul. 12, 2024, as Appl. No. 18/771,817.
Application 18/771,817 is a division of application No. 17/737,854, filed on May 5, 2022, granted, now 12,057,164.
Claims priority of provisional application 63/220,023, filed on Jul. 9, 2021.
Prior Publication US 2024/0371442 A1, Nov. 7, 2024
Int. Cl. G11C 7/00 (2006.01); G11C 11/16 (2006.01); G11C 13/00 (2006.01)
CPC G11C 13/0069 (2013.01) [G11C 11/1673 (2013.01); G11C 11/1675 (2013.01); G11C 13/004 (2013.01); G11C 13/0004 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a memory storage having bit cells, wherein a bit cell of the bit cells has a more preferred state and a less preferred state;
a write path switch configured to have a connection state determined by a reliability indicator;
a write terminal configured to receive a data of a data set;
a write driver having an input configured to receive an input data from the write terminal through either a first write path or a second write path as determined by the connection state of the write path switch, the write driver is operative to write an input bit of the input data into the bit cell as a stored bit;
wherein the input data received through the first write path is configured to be equal to the data at the write terminal, and the input data received through the second write path is configured to be a bitwise complement of the data at the write terminal; and
wherein the reliability indicator is configured to be set based on a majority bit value in the data or based on a minority bit value in the data.