US 12,334,150 B2
Synaptic array for field-training-capable in-memory computing using non-volatile memory technologies
Binh Quang Le, San Jose, CA (US)
Assigned to San Jose State University Research Foundation, San Jose, CA (US)
Filed by San Jose State University Research Foundation, San Jose, CA (US)
Filed on Mar. 23, 2023, as Appl. No. 18/188,978.
Claims priority of provisional application 63/325,053, filed on Mar. 29, 2022.
Prior Publication US 2023/0317163 A1, Oct. 5, 2023
Int. Cl. G11C 13/00 (2006.01); G11C 11/54 (2006.01)
CPC G11C 13/0069 (2013.01) [G11C 11/54 (2013.01); G11C 13/0007 (2013.01); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G11C 13/004 (2013.01); G11C 2013/0045 (2013.01); G11C 2213/72 (2013.01); G11C 2213/74 (2013.01); G11C 2213/79 (2013.01); G11C 2213/82 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An edge device comprising a Deep Neural Network (DNN), the DNN comprising:
a plurality of input nodes;
a plurality of output nodes; and
weights provided between the input nodes and the output nodes, the weights provided by a memory array, the memory array comprising a plurality of non-volatile memory cells, each non-volatile memory cell having a non-volatile memory coupled to a switch, each non-volatile memory cell coupled to:
a wordline coupled to the switch for selection of the non-volatile memory cell,
an input line to provide a current to the non-volatile memory cell through a resistor, and
an output line to which the non-volatile memory cell provides a current component of an output dependent on whether the non-volatile memory cell is in an on state, in which a resistance of the non-volatile memory is substantially less than the resistance of the resistor to which the non-volatile memory cell is connected, or an off state, in which the resistance of the non-volatile memory is substantially greater than the resistance of the resistor to which the non-volatile memory cell is connected.