US 12,334,149 B2
Data reading circuit and data reading circuit control method
Ziyue Zhang, Shenzhen (CN); Yue Pan, Shenzhen (CN); and Mingen Bu, Shanghai (CN)
Assigned to HUAWEI TECHNOLOGIES CO., LTD., Shenzhen (CN)
Filed by HUAWEI TECHNOLOGIES CO., LTD., Guangdong (CN)
Filed on Apr. 9, 2023, as Appl. No. 18/297,633.
Application 18/297,633 is a continuation of application No. PCT/CN2020/123767, filed on Oct. 26, 2020.
Prior Publication US 2023/0245700 A1, Aug. 3, 2023
Int. Cl. G11C 11/00 (2006.01); G11C 7/08 (2006.01); G11C 13/00 (2006.01)
CPC G11C 13/004 (2013.01) [G11C 7/08 (2013.01); G11C 2013/0045 (2013.01); G11C 2013/0054 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A data reading circuit for reading a resistive random access memory, comprising:
a sense amplifier;
a first switch;
a second switch;
a current trimming circuit;
a data cell; and
a reference cell;
wherein a first input terminal of the sense amplifier is coupled to a first terminal of the first switch and the data cell, a second input terminal of the sense amplifier is coupled to a first terminal of the second switch and the reference cell, and a second terminal of the first switch is coupled to a second terminal of the second switch through the current trimming circuit, and
wherein the current trimming circuit is configured to trim a current of the first input terminal of the sense amplifier when the first switch is turned on, and trim a current of the second input terminal of the sense amplifier when the second switch is turned on.