US 12,334,148 B2
Method of operating memory cell
Kuo-Yu Hsiang, Kaohsiung (TW); and Min-Hung Lee, Taipei (TW)
Assigned to NATIONAL TAIWAN UNIVERSITY, Taipei (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW); NATIONAL TAIWAN UNIVERSITY, Taipei (TW); and National Taiwan Normal University, Taipei (TW)
Filed on Mar. 28, 2023, as Appl. No. 18/191,668.
Claims priority of provisional application 63/426,079, filed on Nov. 17, 2022.
Prior Publication US 2024/0170059 A1, May 23, 2024
Int. Cl. G11C 13/00 (2006.01)
CPC G11C 13/0038 (2013.01) [G11C 13/0035 (2013.01); G11C 2213/31 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of operating a memory cell, comprising:
performing a first plurality of bias operations to the memory cell using a first voltage, wherein the memory cell comprises a variable resistance pattern, and the first voltage of each cycle of the first plurality of bias operations has a same first polarity;
determining whether the memory cell reaches a fatigue threshold; and
after the determination determines that the memory cell reaches the fatigue threshold, performing a second plurality of bias operations to the memory cell using a second voltage, wherein the second voltage of each cycle of the second plurality of bias operations has a same second polarity, and the second polarity is opposite to the first polarity, the first voltage and the second voltage have a same amplitude variation.