| CPC G11C 11/419 (2013.01) [G11C 5/14 (2013.01)] | 20 Claims |
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1. An apparatus, comprising:
a storage array circuit including a plurality of storage circuits, wherein subsets of the plurality of storage circuits are configured to store data in response to activation of corresponding word lines of a plurality of word lines; and
a control circuit configured to:
activate a particular word line of the plurality of word lines using a received write address and in response to an activation of a write command and to a first transition of a global clock signal from a first logical value to a second logical value; and
activate a particular local clock signal of a plurality of local clock signals using the particular word line;
wherein write data received with the write address is provided to the plurality of storage circuits, wherein a particular storage circuit of the plurality of storage circuits that is coupled to the particular word line includes a first stage circuit, a second stage circuit, and a power gating circuit, wherein the particular storage circuit is configured to transfer a portion of the write data from the first stage circuit to the second stage circuit in response to an activation of the particular local clock signal; and
wherein the power gating circuit is configured to:
couple at least a portion of the first stage circuit to a power supply node in response to an activation of the particular word line; and
de-couple the at least a portion of the first stage circuit from the power supply node in response to a de-activation of the particular word line.
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