US 12,334,145 B2
Bitcell supporting bit-write-mask function
Hidehiro Fujiwara, Hsinchu (TW); Yen-Huei Chen, Hsinchu (TW); and Yi-Hsin Nien, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Apr. 17, 2023, as Appl. No. 18/301,876.
Application 17/456,149 is a division of application No. 16/693,677, filed on Nov. 25, 2019, granted, now 11,183,234, issued on Nov. 23, 2021.
Application 18/301,876 is a continuation of application No. 17/456,149, filed on Nov. 22, 2021, granted, now 11,631,456.
Prior Publication US 2023/0253035 A1, Aug. 10, 2023
Int. Cl. G11C 11/412 (2006.01); G11C 11/419 (2006.01); H10B 10/00 (2023.01)
CPC G11C 11/419 (2013.01) [G11C 11/412 (2013.01); H10B 10/12 (2023.02)] 19 Claims
OG exemplary drawing
 
1. A memory cell, comprising:
a data storage having an input and an output, and adapted to maintain at the output an output signal in a plurality of states in response to receiving an input signal in a respectively plurality of states at the input; and
an access control adapted to input data to, and output data from, the data storage, the access control comprising:
a read-access control adapted to receive from a read-access control line a read-access control signal selectable between at least one read-enable state and at least one read-disable state, and to output to a read-signal line a signal corresponding to the output signal at the output of the data storage when the read-access control signal is in the read-enable state; and
a first write-access control adapted to receive from a first write-access control line a first write-access control signal selectable between at least one write-enable state and at least one write-disable state and to permit a data signal from a write-signal line to be written to the input of the data storage in response at least in part to the first write-access control signal being in one of the write-enable and write-disable states;
the data storage having a first threshold signal level, wherein the data storage changes the state of the output signal only when the input signal has a level of at least the first threshold signal level;
the read-access control having a second threshold signal level, wherein the read-access control outputs to the read-signal line a signal corresponding to the output signal at the output of the data storage only when the read-access control signal has a level of at least the second threshold signal level;
the write-access control having a third threshold signal level, wherein the write-access control permits a data signal from a write-signal line to be written to the input of the data storage only when the first write-access control signal has a level of at least the third threshold signal level,
the first threshold signal level being different from the second and third threshold signal levels.