US 12,334,141 B2
Write timing compensation
Kang-Yong Kim, Boise, ID (US); Keun Soo Song, Eagle, ID (US); and Hyun Yoo Lee, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 27, 2022, as Appl. No. 17/804,422.
Claims priority of provisional application 63/212,548, filed on Jun. 18, 2021.
Prior Publication US 2022/0406365 A1, Dec. 22, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/40 (2006.01); G11C 11/4074 (2006.01); G11C 11/4076 (2006.01); G11C 11/4093 (2006.01); G11C 11/4096 (2006.01)
CPC G11C 11/4096 (2013.01) [G11C 11/4074 (2013.01); G11C 11/4076 (2013.01); G11C 11/4093 (2013.01)] 23 Claims
OG exemplary drawing
 
1. An apparatus comprising:
an interface for a memory interconnect;
control logic configured to transmit, through the interface, write data to the memory interconnect;
a power management integrated circuit (PMIC) configured to provide power at an output of the PMIC with an adjustable voltage;
a power rail operably coupled to the output of the PMIC; and
a write timing compensation circuit comprising:
an input node operably coupled to a digital-to-analog block of the control logic;
an output node operably coupled to a data signal bus of the memory interconnect; and
an adjustable delay circuit coupled between the input node and the output node, the adjustable delay circuit comprising a set of buffers connected in series, each buffer of the set of buffers having an output coupled to a first respective switch configured to selectively couple the output of the buffer to the output node of the write timing compensation circuit and a power input coupled to a second respective switch configured to selectively couple to the power input of the buffer to the power rail at which the power is provided with the adjustable voltage.