| CPC G11C 11/4091 (2013.01) [G11C 11/4074 (2013.01); G11C 11/4093 (2013.01)] | 20 Claims |
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1. A semiconductor memory device, comprising:
a memory bank arranged into first through nth split regions containing at least one memory cell sub-array within each split region, where n is a positive integer greater than one;
first through nth global input/output (GIO) split lines electrically coupled to the first through nth split regions, respectively;
first through n−1th connection control transistors having gate terminals responsive to respective connection control signals, said first connection control transistor configured to electrically short the first and second GIO split lines together when enabled by a corresponding connection control signal, and said n−1th connection control transistor configured to electrically short the n−1th and nth GIO split lines together when enabled by a corresponding connection control signal;
a GIO sense amplifier electrically coupled to said memory bank; and
a control circuit configured to reduce power consumption within the memory device during an operation to transfer read data from a selected one of the memory cell sub-arrays to said GIO sense amplifier, by selectively driving the connection control signals provided to the second through n−1th connection control transistors such that only a subset of the first through nth GIO split lines are electrically coupled together in series when the read data is from the second through nth split regions.
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