CPC G11C 11/4087 (2013.01) [G11C 11/4085 (2013.01); G11C 11/4091 (2013.01)] | 20 Claims |
1. A memory device, comprising:
one or more memory blocks, wherein each memory block comprises:
a plurality of first sense amplifier circuits;
a plurality of row segments, the row segments and the first sense amplifier circuits being arranged alternately along a first direction, wherein each row segment comprises a plurality of memory cells arranged in rows and columns, and each column of memory cells extends in the first direction; the row segments are divided into N groups of row segments, and N is greater than one; and
a plurality of row decoders, coupled to the row segments respectively, the row decoders being divided into N groups of row decoders.
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