| CPC G11C 11/408 (2013.01) [G06F 12/06 (2013.01); G11C 7/24 (2013.01); G11C 29/18 (2013.01); G11C 29/56004 (2013.01)] | 42 Claims |
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1. A method comprising:
monitoring, by a memory controller coupled to a memory device comprising a plurality of memory dies, a timer from a previous configuration of address scramble patterns of the memory device;
migrating data from the memory device to another memory device in response to the timer reaching a threshold that enables the memory controller to change the address scramble patterns of the memory device;
determining, by the memory controller, that the address scramble patterns of the memory device are in a configurable state after the data has been migrated from the memory device to the other memory device;
selecting, from a plurality of address scramble patterns implemented by the memory controller, a first address scramble pattern for a first memory die of the plurality of memory dies, the first address scramble pattern providing a first logical-to-physical mapping for row addresses of the first memory die of the memory device;
selecting, from the plurality of address scramble patterns implemented by the memory controller, a second address scramble pattern for a second memory die of the plurality of memory dies, the second address scramble pattern providing a second logical-to-physical mapping for row addresses of the second memory die of the memory device that is different from the first logical-to-physical mapping for row addresses of the first memory die of the memory device;
configuring, by the memory controller, the first memory die of the memory device to use the first address scramble pattern for logical-to-physical mapping of the row addresses associated with access of the first memory die of the memory device; and
configuring, by the memory controller, the second memory die of the memory device to use the second address scramble pattern for logical-to-physical mapping of the row addresses associated with access of the second memory die of the memory device.
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