	US 12,334,137 B2
	Maximum memory clock estimation procedures
Erik V. Pohlmann, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 6, 2022, as Appl. No. 17/929,970.
Claims priority of provisional application 63/365,684, filed on Jun. 1, 2022.
Prior Publication US 2023/0395125 A1, Dec. 7, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/04 (2006.01); G11C 7/22 (2006.01); G11C 11/406 (2006.01); G11C 11/4076 (2006.01); G11C 11/4093 (2006.01); G11C 29/02 (2006.01)

CPC G11C 11/4076 (2013.01) [G06F 1/04 (2013.01); G11C 7/222 (2013.01); G11C 11/40615 (2013.01); G11C 11/4093 (2013.01); G11C 29/023 (2013.01); G11C 29/028 (2013.01)]

25 Claims

1. A method, comprising:

truncating a value of a first parameter associated with a first duration for a clock coupled with a memory array to perform a clock cycle;

estimating a value of a second parameter that is inversely proportional to the truncated value of the first parameter and directly proportional to a truncated value of a third parameter, wherein the third parameter is a nominal duration for performing a memory operation;

determining a quantity of clock cycles associated with a maximum duration for accessing one or more memory cells of the memory array based at least in part on truncating the second parameter; and

accessing the one or more memory cells of the memory array based at least in part on the determined quantity of clock cycles associated with the maximum duration.