US 12,334,136 B2
Independent multi-page read operation enhancement technology
Naveen Prabhu Vittal Prabhu, Folsom, CA (US); Aliasgar S. Madraswala, Folsom, CA (US); Bharat Pathak, Folsom, CA (US); Binh Ngo, Folsom, CA (US); Netra Mahuli, Folsom, CA (US); and Ahsanur Rahman, Santa Clara, CA (US)
Assigned to SK Hynix NAND Product Solutions Corp., Rancho Cordova, CA (US)
Filed by Intel NDTM US LLC, Santa Clara, CA (US)
Filed on Jun. 24, 2021, as Appl. No. 17/357,466.
Prior Publication US 2022/0415380 A1, Dec. 29, 2022
Int. Cl. G11C 16/04 (2006.01); G06F 3/06 (2006.01); G11C 11/4076 (2006.01); G11C 11/4096 (2006.01)
CPC G11C 11/4076 (2013.01) [G06F 3/0659 (2013.01); G11C 11/4096 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a NAND die; and
a controller including logic coupled to one or more substrates, the logic to:
send a first command to the NAND die,
send first address information to the NAND die,
send a second command to the NAND die, wherein the first command and the second command define a first command sequence, and wherein the first command sequence and the first address information signal a beginning of a first asynchronous read request from a first plurality of planes, and
send the first command sequence and third address information to the NAND die, wherein the first command sequence and the third address information signal a beginning of a second asynchronous read request from a second plurality of planes, and wherein the first and second asynchronous read requests are performed concurrently on multiple plane groups, wherein each plane group comprises multiple planes.