| CPC G11C 11/2275 (2013.01) [G11C 11/223 (2013.01); G11C 11/2255 (2013.01); G11C 11/2257 (2013.01); G11C 11/2273 (2013.01); G11C 11/2297 (2013.01); H10B 51/20 (2023.02); H10B 51/30 (2023.02)] | 20 Claims |
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1. A memory device, comprising:
a plurality of memory cells;
at least two power supplies in a first power domain configured to provide a first voltage and a second voltage for switching states of memory cells in the plurality of memory cells;
at least one power supply in a second power domain configured to provide a third voltage for logic operations and data signaling; and
a control circuit configured to provide the first voltage and the second voltage to the plurality of memory cells for switching the states of the memory cells in the plurality of memory cells,
wherein the control circuit is electrically coupled to the plurality of memory cells through word lines, bit lines, and source lines, and the control circuit is configured to provide the first voltage to the word lines and the second voltage to the bit lines and/or the source lines for switching the states of the memory cells, and
wherein, in a read operation, the control circuit is configured to provide a positive voltage as the first voltage to a word line corresponding to a selected memory cell, a fourth voltage to the bit line of the selected memory cell, and zero volts to the source line of the selected memory cell.
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