US 12,334,127 B2
Non-linear polar material based multi-capacitor high density bit-cell
Rajeev Kumar Dokania, Beaverton, OR (US); Mustansir Yunus Mukadam, Seattle, WA (US); Erik Unterborn, Cary, NC (US); Pramod Kolar, Cary, NC (US); Amrita Mathuriya, Portland, OR (US); Debo Olaosebikan, San Francisco, CA (US); Tanay Gosavi, Portland, OR (US); Noriyuki Sato, Hillsboro, OR (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to Kepler Computing Inc., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Jan. 30, 2023, as Appl. No. 18/161,808.
Prior Publication US 2024/0257854 A1, Aug. 1, 2024
Int. Cl. G11C 11/22 (2006.01)
CPC G11C 11/221 (2013.01) [G11C 11/2255 (2013.01); G11C 11/2257 (2013.01); G11C 11/2259 (2013.01); G11C 11/2273 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a plurality of capacitors, wherein an individual capacitor of the plurality of capacitors is coupled to a node and an individual plate-line;
a first transistor coupled to the node;
a second transistor coupled in series with the first transistor, wherein the second transistor is coupled to a sense-line; and
a third transistor coupled to the node and a bit-line, wherein the third transistor is controllable by a word-line, and wherein the word-line is parallel to the individual plate-line.