US 12,334,109 B2
Video processing circuit and associated video processing method
Xiao-Ding Zhu, Shanghai (CN)
Assigned to SIGMASTAR TECHNOLOGY LTD., Fujian (CN)
Filed by SigmaStar Technology Ltd., Fujian (CN)
Filed on Mar. 13, 2023, as Appl. No. 18/182,517.
Claims priority of application No. 202211243290.3 (CN), filed on Oct. 11, 2022.
Prior Publication US 2024/0119966 A1, Apr. 11, 2024
Int. Cl. G11B 20/10 (2006.01); G11B 20/00 (2006.01)
CPC G11B 20/10527 (2013.01) [G11B 20/00007 (2013.01); G11B 2020/00072 (2013.01); G11B 2020/10666 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A video processing circuit, coupled to a memory chip, comprising:
an image processing circuit, comprising:
a first channel and a second channel, the first channel and the second channel sharing an input port, wherein the first channel processes first image data to generate first processed image data, and the second channel processes second image data to generate second processed image data; and
a compression circuit, configured to compress the first processed image data and the second processed image data to generate first compressed image data and second compressed image data, respectively;
wherein a memory block in the memory chip is configured as a ring buffer, which is shared by the first channel and the second channel to store the first compressed image data and the second compressed image data,
wherein the image processing circuit further comprises:
a write direct memory access (WDMA) circuit, coupled between the compression circuit and the ring buffer, and configured to write the first compressed image data and the second compressed image data to the ring buffer;
wherein the WDMA circuit establishes a write data table comprising a plurality of entries, each of which records information of one set of data written to the ring buffer.