US 12,334,033 B2
Active matrix substrate and display device
Satoshi Horiuchi, Kameyama (JP); Akane Sugisaka, Kameyama (JP); Seiya Kawamorita, Kameyama (JP); and Shinji Matsubara, Kameyama (JP)
Assigned to Sharp Display Technology Corporation, Kameyama (JP)
Filed by Sharp Display Technology Corporation, Kameyama (JP)
Filed on Aug. 22, 2023, as Appl. No. 18/236,906.
Claims priority of application No. 2022-151995 (JP), filed on Sep. 22, 2022.
Prior Publication US 2024/0105139 A1, Mar. 28, 2024
Int. Cl. G09G 3/36 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01)
CPC G09G 3/3677 (2013.01) [G02F 1/136286 (2013.01); G02F 1/1368 (2013.01); G09G 2310/08 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An active matrix substrate comprising:
a substrate;
a plurality of thin film transistors formed in a pixel region of the substrate;
a gate line group including a plurality of gate lines respectively connected to the plurality of thin film transistors;
a first gate drive circuit configured to supply a gate signal to the gate line group from a first direction;
a second gate drive circuit configured to supply a gate signal to the gate line group from a second direction opposite the first direction;
a first control signal line connected to the first gate drive circuit;
a second control signal line connected to the second gate drive circuit;
a first gate terminal connected to the first control signal line, the first gate terminal configured to supply a control signal to the first control signal line;
a second gate terminal connected to the second control signal line, the second gate terminal configured to supply a control signal to the second control signal line;
a first connection line configured to connect the first control signal line and the second control signal line; and
a first input terminal disposed on one of the first control signal line, the second control signal line, and the first connection line.