US 12,334,022 B2
Shift register unit, gate driving circuit, display device and driving method
Xuehuan Feng, Beijing (CN); Yongqian Li, Beijing (CN); and Hao Liu, Beijing (CN)
Assigned to HEFEI BOE JOINT TECHNOLOGY CO., LTD., Hefei (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Filed by HEFEI BOE JOINT TECHNOLOGY CO., LTD., Hefei (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Filed on Mar. 27, 2024, as Appl. No. 18/618,413.
Application 18/618,413 is a continuation of application No. 18/108,730, filed on Feb. 13, 2023, granted, now 11,984,085.
Application 18/108,730 is a continuation of application No. 17/490,054, filed on Sep. 30, 2021, granted, now 11,615,743, issued on Mar. 28, 2023.
Application 17/490,054 is a continuation of application No. 16/766,470, granted, now 11,164,516, issued on Nov. 2, 2021, previously published as PCT/CN2019/128655, filed on Dec. 26, 2019.
Claims priority of application No. 201910048927.5 (CN), filed on Jan. 18, 2019.
Prior Publication US 2024/0242680 A1, Jul. 18, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G09G 3/3266 (2016.01); G09G 3/3225 (2016.01); G11C 19/28 (2006.01)
CPC G09G 3/3266 (2013.01) [G09G 3/3225 (2013.01); G11C 19/28 (2013.01); G09G 2310/0286 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A shift register unit, comprising a first sub-circuit, a leakage prevention circuit and a blanking input sub-circuit, wherein
the first sub-circuit comprises a first input circuit and a first output circuit, the first input circuit is configured to control a level of a first node in response to a first input signal, and the first output circuit is configured to output a shift signal and a first output signal under control of the level of the first node;
the blanking input sub-circuit comprises a first transmission circuit, the first transmission circuit comprises a first transmission transistor and a second transmission transistor;
the leakage prevention circuit is connected to the first node, a first voltage and a leakage prevention node;
a gate electrode of the first transmission transistor is configured to receive a first clock signal, a first electrode of the first transmission transistor is connected to a fourth node, and a second electrode of the first transmission transistor is connected to the leakage prevention node; and
a gate electrode of the second transmission transistor is configured to receive the first clock signal, a first electrode of the second transmission transistor is connected to the leakage prevention node, and a second electrode of the second transmission transistor is connected to the first node.