US 12,334,020 B2
Shift register unit, gate driving circuit, and gate driving method
Xuehuan Feng, Beijing (CN); and Dacheng Zhang, Beijing (CN)
Assigned to Hefei BOE Joint Technology Co., Ltd., Anhui (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Appl. No. 18/031,560
Filed by Hefei BOE Joint Technology Co., Ltd., Anhui (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed May 24, 2022, PCT No. PCT/CN2022/094697
§ 371(c)(1), (2) Date Apr. 12, 2023,
PCT Pub. No. WO2023/225847, PCT Pub. Date Nov. 30, 2023.
Prior Publication US 2024/0371328 A1, Nov. 7, 2024
Int. Cl. G09G 3/3266 (2016.01); G11C 19/28 (2006.01)
CPC G09G 3/3266 (2013.01) [G11C 19/28 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/061 (2013.01); G09G 2310/08 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A shift register unit, comprising:
a sensing control circuit connected to a sensing signal input terminal, a random signal input terminal, and a sensing control node, and configured to write a signal provided by the sensing signal input terminal to the sensing control node in response to control of an active level signal provided by the random signal input terminal;
a first sensing input circuit connected to a clock control signal input terminal, the sensing control node, and a first pull-up node, and configured to write a signal provided by the clock control signal input terminal to the first pull-up node only in response to control of an active level signal at the sensing control node; and
a first driving output circuit connected to the first pull-up node, a first driving clock signal input terminal, and a first driving signal output terminal, and configured to write a signal provided by the first driving clock signal input terminal to the first driving signal output terminal in response to control of an active level signal at the first pull-up node,
wherein the shift register unit further comprises:
a first display input circuit connected to a display signal input terminal, a third power supply terminal, and the first pull-up node, and configured to write an active level signal provided by the third power supply terminal to the first pull-up node in response to control of an active level signal provided by the display signal input terminal;
a second driving output circuit connected to the first pull-up node, a second driving clock signal input terminal, and a second driving signal output terminal, and configured to write a signal provided by the second driving clock signal input terminal to the second driving signal output terminal in response to control of an active level signal at the first pull-up node; and
a first cascade output circuit connected to the first pull-up node, a first cascade clock signal input terminal, and a first cascade signal output terminal, and configured to write a signal provided by the first cascade clock signal input terminal to the first cascade signal output terminal in response to control of an active level signal at the first pull-up node.