| CPC G09G 3/3241 (2013.01) [H10K 59/879 (2023.02); G09G 3/2096 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/08 (2013.01); G09G 2380/10 (2013.01)] | 23 Claims |

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1. A display apparatus comprising:
a mode controller configured to generate a first control signal and a second control signal;
a gate drive circuit configured to generate a light-emitting signal, a first scan signal, and a second scan signal;
a shared circuit connected to a reference voltage line and configured to provide a reference voltage, wherein the shared circuit includes a first transistor configured to operate based on the first scan signal, and a second transistor connected to the first transistor in series and configured to operate based on the second scan signal; and
a first pixel circuit connected to the mode controller and the gate drive circuit,
wherein the first pixel circuit comprises:
a driving transistor;
a third transistor configured to operate based on the light-emitting signal and connected to the second transistor;
a fourth-first transistor configured to operate based on the first control signal;
a fourth-second transistor configured to operate based on the second control signal;
a first light-emitting element connected to the fourth-first transistor;
a second light-emitting element connected to the fourth-second transistor; and
a capacitor connected to the first transistor, the second transistor, the third transistor, and the driving transistor.
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