| CPC G09G 3/32 (2013.01) [G09G 3/3233 (2013.01); G09G 2300/0452 (2013.01); G09G 2300/0852 (2013.01); G09G 2310/066 (2013.01); G09G 2320/0242 (2013.01); G09G 2320/045 (2013.01); G09G 2320/0633 (2013.01); G09G 2320/064 (2013.01)] | 19 Claims |

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1. A display module comprising a plurality of pixels,
wherein each of the plurality of pixels comprises a plurality of subpixels of different colors that are disposed in a matrix form, and
wherein each of the plurality of subpixels comprises:
an inorganic light emitting element;
a constant current generator which provides a constant current to the inorganic light emitting element; and
a pulse width modulation (PWM) circuit comprising a first depletion mode driving transistor and an internal compensation circuit to compensate a threshold voltage of the first depletion mode driving transistor,
wherein the internal compensation circuit obtains the threshold voltage of the first depletion mode driving transistor corresponding to a difference between an input voltage inputted to a gate of the first depletion mode driving transistor and a voltage outputted from a source terminal while the first depletion mode driving transistor operates as a source follower,
wherein the PWM circuit obtains a PWM data voltage in which the threshold voltage of the first depletion mode driving transistor is compensated, and controls a time during which the constant current flows through the inorganic light emitting element based on the compensated PWM data voltage,
wherein the PWM circuit comprises a first capacitor connected between a gate terminal and the source terminal of the first depletion mode driving transistor and configured to receive a reference signal through a node A connecting the gate terminal of the first depletion mode driving transistor to the first capacitor, and a second capacitor connected between the gate terminal and the source terminal of the first depletion mode driving transistor and configured to receive a data signal through a node B connecting the second capacitor to the source terminal of the first depletion mode driving transistor and the first capacitor, and
wherein one end of the second capacitor is directly connected to each of the node B, the first capacitor, and the source terminal of the first depletion mode driving transistor, and another end of the second capacitor is directly connected to each of the node A, the first capacitor, and the gate terminal of the first depletion mode driving transistor.
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