| CPC G09G 3/2096 (2013.01) [G09G 3/3233 (2013.01); H03K 5/13 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/08 (2013.01)] | 16 Claims |
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1. A clock generator comprising:
a first clock generation circuit configured to output a clock, data synchronized with the clock, and a timing control signal;
a first wiring connected to the first clock generation circuit to serially transmit the clock;
a second wiring connected to the first clock generation circuit to serially transmit the data;
a third wiring connected to the first clock generation circuit to serially transmit pulses of the timing control signal;
a second clock generation circuit connected to the first clock generation circuit through the first wiring, the second wiring, and the third wiring, and configured to count the clock based on the data and causes a pulse of pre-clocks to rise and fall to generate the pre-clocks in which phases are sequentially shifted based on the data and the clock; and
a clock adjustment circuit configured to receive the pulses of the timing control signal and the pre-clocks and output an output clock,
wherein:
a frequency of each of the timing control signal and the pre-clocks is lower than a frequency of the clock and the data,
the timing control signal includes at least one pulse overlapped with any one of the pre-clocks, and
the clock adjustment circuit is configured to adjust at least one of a rising time point, a pulse width, or a falling time point of a pulse of a pre-clock based on a pulse of the timing control signal to generate the output clock.
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