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1. A display panel, wherein the display panel comprises a plurality of pixel circuits, and each of the plurality of the pixel circuits comprises: a mirror current receiving module, wherein the mirror current receiving module comprises N mirror current receiving units, a control terminal of each of the N mirror current receiving units is connected to one mirror current, and the N mirror current receiving units are respectively connected in series to light-emitting subloops, N being an integer greater than or equal to 2; a digital driving module, wherein the digital driving module comprises N digital driving units, and the N digital driving units are respectively connected in series to the light-emitting subloops; a light-emitting module, wherein the light-emitting module is connected to a light-emitting loop formed by the light-emitting subloops; and wherein each of the N digital driving units comprises: a register and the register comprises: a phase inverter, wherein an input terminal of the phase inverter is connected to the data line; a first storage transistor, wherein a first electrode of the first storage transistor is connected to a power supply positive terminal; a second storage transistor, wherein a first electrode of the second storage transistor is connected to a second electrode of the first storage transistor and the gate of the switching transistor, a second electrode of the second storage transistor is connected to a power supply negative terminal, and a gate of the second storage transistor is connected to a gate of the first storage transistor; a third storage transistor, wherein a first electrode of the third storage transistor is connected to the power supply positive terminal, a second electrode of the third storage transistor is connected to the gate of the first storage transistor, and a gate of the third storage transistor is connected to the second electrode of the first storage transistor; a fourth storage transistor, wherein a first electrode of the fourth storage transistor is connected to the second electrode of the third storage transistor, a second electrode of the fourth storage transistor is connected to the power supply negative terminal, and a gate of the fourth storage transistor is connected to the gate of the third storage transistor; a fifth storage transistor, wherein a first electrode of the fifth storage transistor is connected to the data line, a second electrode of the fifth storage transistor is connected to the gate of the second storage transistor, and a gate of the fifth storage transistor is connected to the scan line; and a sixth storage transistor, wherein a first electrode of the sixth storage transistor is connected to an output terminal of the phase inverter, a second electrode of the sixth storage transistor is connected to the gate of the third storage transistor, and a gate of the sixth storage transistor is connected to the gate of the fifth storage transistor.
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