US 12,333,976 B2
Display device, gate drive circuit, shift register unit and driving method thereof
Xuehuan Feng, Beijing (CN); and Yongqian Li, Beijing (CN)
Assigned to Hefei BOE Joint Technology Co., Ltd., Anhui (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 18/292,284
Filed by Hefei BOE Joint Technology Co., Ltd., Anhui (JP); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed May 16, 2023, PCT No. PCT/CN2023/094550
§ 371(c)(1), (2) Date Jan. 25, 2024,
PCT Pub. No. WO2024/234304, PCT Pub. Date Nov. 21, 2024.
Prior Publication US 2025/0095529 A1, Mar. 20, 2025
Int. Cl. G09G 3/20 (2006.01)
CPC G09G 3/20 (2013.01) [G09G 2310/0267 (2013.01); G09G 2310/0286 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A shift register unit comprising:
an input subcircuit, connected to an input control end and a first node, configured to control a voltage at the first node under voltage control of the input control end;
a signal output subcircuit, connected to the first node and connected to a plurality of signal output ends and a plurality of clock signal ends, the plurality of signal output ends corresponding to the plurality of clock signal ends respectively; the signal output subcircuit being configured to control disconnection and conduction between the clock signal ends and respective signal output ends under voltage control of the first node; a plurality of the signal output ends correspondingly output a plurality of output signals, and the plurality of the output signals being sequentially shifted;
a first control subcircuit, connected to a first control signal end and the first node, configured to control the voltage at the first node under voltage control of the first control signal end; the first control signal end being configured to output a control signal; in one display frame, wherein a cutoff time of an effective voltage interval of a last output signal of the plurality of sequentially shifted output signals is greater than or equal to a starting time of an effective voltage interval of the control signal, and the cutoff time of the effective voltage interval of the last output signal of the plurality of sequentially shifted output signals is less than a cutoff time of the effective voltage interval of the control signal;
a cascade output subcircuit, connected to the first node and a cascade output end, configured to control a voltage at the cascade output end under voltage control of the first node; and
a denoising subcircuit, connected to a second node and reset power ends, and connected to at least one of the cascade output end, the first node and the signal output end, configured to control disconnection and conduction between the reset power end and the signal output end under voltage control of the second node, and configured to control disconnection and conduction between the reset power end and the cascade output end under voltage control of the second node, and further configured to control disconnection and conduction between the reset power supply end and the first node under voltage control of the second node.