US 12,333,422 B2
High-density neuromorphic computing element
Borna J. Obradovic, Leander, TX (US); Titash Rakshit, Austin, TX (US); and Mark S. Rodder, Dallas, TX (US)
Assigned to Samsung Electronics Co., Ltd., Yongin-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Apr. 10, 2024, as Appl. No. 18/632,180.
Application 17/094,356 is a division of application No. 15/488,419, filed on Apr. 14, 2017, granted, now 10,860,923, issued on Dec. 8, 2020.
Application 18/632,180 is a continuation of application No. 18/111,471, filed on Feb. 17, 2023, granted, now 11,983,622.
Application 18/111,471 is a continuation of application No. 17/094,356, filed on Nov. 10, 2020, granted, now 11,586,901, issued on Feb. 21, 2023.
Claims priority of provisional application 62/437,016, filed on Dec. 20, 2016.
Prior Publication US 2024/0256848 A1, Aug. 1, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G06N 3/065 (2023.01); H10B 41/30 (2023.01); H10D 30/01 (2025.01); H10D 30/68 (2025.01); H10D 30/83 (2025.01); H10D 64/01 (2025.01)
CPC G06N 3/065 (2023.01) [H10B 41/30 (2023.02); H10D 30/0411 (2025.01); H10D 30/681 (2025.01); H10D 30/6891 (2025.01); H10D 30/831 (2025.01); H10D 64/035 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method for fabricating a neuromorphic device, the method comprising:
forming, on a substrate, a first floating-gate transistor, the first floating-gate transistor having:
a channel;
a floating gate; and
a control gate; and
forming a second floating-gate transistor, vertically stacked on the first floating-gate transistor in a stacking direction, the second floating-gate transistor having:
a channel directly connected to the channel of the first floating-gate transistor;
a floating gate; and
a control gate directly connected to the control gate of the first floating-gate transistor.