CPC G06N 3/063 (2013.01) [G06F 12/00 (2013.01)] | 20 Claims |
1. A neural processing device comprising:
a plurality of neural cores;
a shared memory shared by the plurality of neural cores; and
at least one transactional memory,
wherein the at least one transactional memory is configured to:
receive a memory access request directed to the shared memory from at least one of the plurality of neural cores,
receive a memory access scenario for a plurality of memory access operation groups, and
perform at least one of buffer the received memory access request and commit the received memory access request, in response to a determination of whether the received memory access request belongs to a current memory access operation group among the plurality of memory access operation groups.
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