US 12,333,418 B2
Method and device with neural network implementation
Hyeongseok Yu, Seoul (KR); Hyeonuk Sim, Iksan-si (KR); and Jongeun Lee, Ulsan (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR); and UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY), Ulsan (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR); and UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY), Ulsan (KR)
Filed on Oct. 18, 2023, as Appl. No. 18/489,209.
Application 18/489,209 is a continuation of application No. 16/893,560, filed on Jun. 5, 2020, granted, now 11,829,862.
Claims priority of application No. 10-2019-0162910 (KR), filed on Dec. 9, 2019.
Prior Publication US 2024/0046082 A1, Feb. 8, 2024
Int. Cl. G06F 15/76 (2006.01); G06N 3/04 (2023.01); G06N 3/063 (2023.01)
CPC G06N 3/063 (2013.01) [G06N 3/04 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A neural network device, comprising:
an on-chip buffer memory configured to store an input feature map of a first layer of a neural network;
a local bus connecting the on-chip buffer memory to a computational circuit;
the computational circuit configured to receive the input feature map of the first layer as read from a single port of the on-chip buffer memory, and as transmitted from the single port to the computational circuit via the local bus, and perform a neural network operation on the input feature map of the first layer to output an output feature map of the first layer corresponding to the input feature map of the first layer; and
a controller configured to control transmission of the output feature map of the first layer to be outputted from the computational circuit via the local bus to the on-chip buffer memory to store the output feature map of the first layer and the input feature map of the first layer together in the on-chip buffer memory,
wherein the output feature map of the first layer is reused, from the on-chip buffer memory, as an input feature map for a neural network operation of a second layer subsequent to the first layer,
wherein, when a read operation of the input feature map of the first layer and a write operation of the output feature map of the first layer are simultaneously requested, an order of the read operation and the write operation are adjusted on the local bus, to prevent a collision between the read operation and the write operation in the single port,
wherein the computational circuit is further configured to perform the neural network operation based on one or more operation loops,
wherein the controller is further configured to perform the read operation of reading data constituting, at least, a portion of the input feature map of the first layer from the on-chip buffer memory through the single port at each cycle in which each of the one or more operation loops is executed, and
when the write operation for writing data constituting, at least, a portion of the output feature map of the first layer to the on-chip buffer memory through the single port is requested at a timing at which the read operation is to be performed, the write operation is performed in preference to the read operation.