US 12,333,416 B2
Integrated circuit chip apparatus
Shaoli Liu, Beijing (CN); Xinkai Song, Beijing (CN); Bingrui Wang, Beijing (CN); Yao Zhang, Beijing (CN); and Shuai Hu, Beijing (CN)
Assigned to CAMBRICON TECHNOLOGIES CORPORATION LIMITED, Beijing (CN)
Filed by CAMBRICON TECHNOLOGIES CORPORATION LIMITED, Beijing (CN)
Filed on Jan. 4, 2024, as Appl. No. 18/404,878.
Application 18/404,878 is a continuation of application No. 17/688,844, filed on Mar. 7, 2022, granted, now 11,900,241.
Application 17/688,844 is a continuation of application No. 16/721,885, filed on Dec. 19, 2019, granted, now 11,308,389, issued on Apr. 19, 2022.
Application 16/721,885 is a continuation of application No. PCT/CN2019/073453, filed on Jan. 28, 2019.
Claims priority of application No. 201711343642.1 (CN), filed on Dec. 14, 2017; application No. 201711346333.X (CN), filed on Dec. 14, 2017; application No. 201711347310.0 (CN), filed on Dec. 14, 2017; application No. 201711347406.7 (CN), filed on Dec. 14, 2017; application No. 201711347407.1 (CN), filed on Dec. 14, 2017; application No. 201711347408.6 (CN), filed on Dec. 14, 2017; and application No. 201711347767.1 (CN), filed on Dec. 14, 2017.
Prior Publication US 2024/0152741 A1, May 9, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06N 3/063 (2023.01); G06F 7/483 (2006.01); G06F 7/544 (2006.01); G06F 17/15 (2006.01); G06F 17/16 (2006.01); G06N 3/04 (2023.01); G06N 3/06 (2006.01); G06N 3/08 (2023.01); H01L 25/065 (2023.01)
CPC G06N 3/063 (2013.01) [G06F 7/483 (2013.01); G06F 7/5443 (2013.01); G06F 17/153 (2013.01); G06F 17/16 (2013.01); G06N 3/04 (2013.01); G06N 3/06 (2013.01); G06N 3/08 (2013.01); H01L 25/065 (2013.01); G06F 2207/4824 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit chip apparatus, comprising:
a main processing circuit configured to:
convert data from an original data type to a target data type when the target data type is different from the original data type, wherein one of the original data type and the target data type is a floating point data type and the other is a fixed point data type; and
transfer the data in the target data type and a computation instruction to a plurality of basic processing circuits; and
the plurality of basic processing circuits configured to:
perform a first set of neural network computations on the data transferred by the main processing circuit in the target data type according to the computation instruction to obtain a plurality of computation results; and
transfer the plurality of computations results to the main processing circuit,
wherein the main processing circuit is further configured to perform a second set of neural network computations on the computation results.