US 12,333,357 B2
Memory bit cell for in-memory computation
Michael A. Dreesen, Austin, TX (US); Ajay Bhatia, Saratoga, CA (US); Michael R. Seningen, Austin, TX (US); Greg M. Hess, Mountain View, CA (US); and Siddhesh Gaiki, Cupertino, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on May 11, 2021, as Appl. No. 17/317,844.
Claims priority of provisional application 63/083,824, filed on Sep. 25, 2020.
Prior Publication US 2022/0101914 A1, Mar. 31, 2022
Int. Cl. G06G 7/16 (2006.01); G06F 7/523 (2006.01); G06F 17/16 (2006.01); G11C 11/419 (2006.01); G06F 7/544 (2006.01)
CPC G06G 7/16 (2013.01) [G06F 7/523 (2013.01); G06F 17/16 (2013.01); G11C 11/419 (2013.01); G06F 7/5443 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a sign data storage cell configured to:
store a sign value associated with a weight value; and
couple, based on the sign value, either a compute word line or a complement compute word line to a compute select line;
a plurality of compute data storage cells, wherein a given compute data storage cell includes a capacitor, and wherein the given compute data storage cell is configured to:
store a corresponding bit of the weight value; and
couple, based on the corresponding bit and a voltage level of the compute select line, a respective amount of charge onto a compute bit line via the capacitor;
a control circuit configured to generate, using an operand value, respective voltage levels on the compute word line and the complement compute word line; and
an analog-to-digital converter circuit configured to generate, based on a voltage level of the compute bit line, a plurality of output bits whose value is indicative of a product of the operand value and the weight value.