CPC G06F 9/5027 (2013.01) [G06F 9/4881 (2013.01)] | 18 Claims |
1. An apparatus, comprising:
first and second groups of graphics processor sub-units, wherein the first group of sub-units shares a first cache and the second group of sub-units shares a second cache;
distribution circuitry configured to:
receive a software-specified set of graphics work and a software-indicated mapping of portions of the set of graphics work to groups of graphics processor sub-units; and
assign, based on the mapping, a first subset of the set of graphics work to the first group of graphics sub-units and a second subset of the set of graphics work to the second group of graphics sub-units; and
work sharing control circuitry configured to:
determine that another group of sub-units that share a cache have dispatched all of their assigned portion for the set of graphics work;
update a hardware-implemented finite state machine based on the determination, wherein the hardware finite state machine is implemented using sequential circuitry and combinational circuitry; and
override, based on the update to the hardware-implemented finite state machine, the software-indicated mapping of portions of the set of graphics work to groups of graphics processor sub-units, wherein the override re-assigns part of the first subset of the set of graphics work from the first group of graphics units to the other group of sub-units and the part of the first subset would not have been assigned to the other group of sub-units under the software-indicated mapping.
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