US 12,333,310 B2
Base plus offset addressing for load/store messages
John Wiegert, Aloha, OR (US); Joydeep Ray, Folsom, CA (US); Timothy Bauer, Hillsboro, OR (US); and James Valerio, North Plains, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 28, 2024, as Appl. No. 18/620,217.
Application 18/620,217 is a continuation of application No. 17/949,904, filed on Sep. 21, 2022, granted, now 12,014,183.
Prior Publication US 2024/0330001 A1, Oct. 3, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/38 (2018.01); G06F 9/30 (2018.01); G06F 9/355 (2018.01); G06F 15/78 (2006.01)
CPC G06F 9/3887 (2013.01) [G06F 9/355 (2013.01); G06F 9/3888 (2023.08); G06F 15/7839 (2013.01); G06F 9/30036 (2013.01); G06F 9/30043 (2013.01)] 20 Claims
OG exemplary drawing
 
9. A method comprising:
on a graphics core configured to perform parallel processing operations on a plurality of data elements stored in a memory:
determining byte addresses for the plurality of data elements stored in the memory via memory access circuitry configured to receive offload of memory address calculations for the plurality of data elements from a plurality of processor lanes of processing resources of the graphics core, the byte addresses determined based on a base address, an offset between addresses of data elements of the plurality of data elements, and a scale factor to apply to the offset, wherein the byte addresses are byte granularity addresses of data elements to be processed by the plurality of processor lanes; and
submitting a memory access request to the memory on behalf of the plurality of processor lanes to access the plurality of data elements at the byte addresses determined for the plurality of data elements.