US 12,333,309 B2
Differential pipeline delays in a coprocessor
Jay Fleischman, Fort Collins, CO (US); Michael Estlick, Fort Collins, CO (US); Michael Christopher Sedmak, Fort Collins, CO (US); Erik Swanson, Fort Collins, CO (US); and Sneha V. Desai, Fort Collins, CO (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US)
Filed on Jun. 16, 2023, as Appl. No. 18/211,007.
Application 18/211,007 is a continuation of application No. 15/837,974, filed on Dec. 11, 2017, granted, now 11,709,681.
Prior Publication US 2024/0045694 A1, Feb. 8, 2024
Int. Cl. G06F 9/38 (2018.01)
CPC G06F 9/3867 (2013.01) [G06F 9/3836 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a pipeline comprising a first portion and a second portion; and
a scheduler configured to cause a first subset of bits of an instruction to be provided to the first portion and a second subset of bits of the instruction to the second portion, and to tag the instruction with a set of bits that indicates whether the second subset of the bits of the instruction is to be executed by the pipeline.