US 12,333,308 B2
Method and device for selecting entry of queue in out-of-order processor
Zusong Li, Beijing (CN); and Dandan Huan, Beijing (CN)
Assigned to BEIJING VCORE TECHNOLOGY CO., LTD., Beijing (CN)
Appl. No. 18/580,047
Filed by BEIJING VCORE TECHNOLOGY CO., LTD., Beijing (CN)
PCT Filed Jun. 13, 2023, PCT No. PCT/CN2023/099985
§ 371(c)(1), (2) Date Jan. 17, 2024,
PCT Pub. No. WO2024/146076, PCT Pub. Date Jul. 11, 2024.
Claims priority of application No. 202310017030.2 (CN), filed on Jan. 6, 2023.
Prior Publication US 2025/0085974 A1, Mar. 13, 2025
Int. Cl. G06F 9/38 (2018.01); G06F 9/30 (2018.01)
CPC G06F 9/3856 (2023.08) [G06F 9/30036 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for selecting an entry of a queue in an out-of-order processor, comprising:
acquiring a tag value of each entry in the queue;
generating a mask bit vector of the queue based on the tag value of each entry;
generating an executable bit vector of the queue based on indication information of each entry in the queue, wherein the indication information is configured to indicate whether a corresponding entry satisfies an executable condition;
generating a selection bit vector of the queue based on the mask bit vector and the executable bit vector; and
determining an entry corresponding to a target bit in the selection bit vector as an executable entry, wherein the target bit is a first bit in the selection bit vector, and a value of the first bit is equal to a first preset value.