US 12,333,307 B2
Approach for managing near-memory processing commands from multiple processor threads to prevent interference at near-memory processing elements
Johnathan Alsop, Bellevue, WA (US); Laurent S. White, Austin, TX (US); and Shaizeen Aga, Santa Clara, CA (US)
Assigned to Advanced Micro Devices, Inc., Sant Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Jun. 29, 2022, as Appl. No. 17/853,613.
Prior Publication US 2024/0004653 A1, Jan. 4, 2024
Int. Cl. G06F 9/30 (2018.01); G06F 15/78 (2006.01)
CPC G06F 9/3009 (2013.01) [G06F 9/3004 (2013.01); G06F 9/30101 (2013.01); G06F 15/7821 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A memory controller configured to:
issue one or more near-memory processing commands for a first processor thread; and
defer issuance of one or more near-memory processing commands for a second processor thread by performing one of:
moving the one or more near-memory processing commands for the second processor thread into deferred command storage, or
changing a pointer to skip the one or more near-memory processing commands for the second processor thread;
wherein the one or more near-memory processing commands for the first processor thread and the one or more near-memory processing commands for the second processor thread are directed to a same memory element.