US 12,333,306 B2
High performance constant cache and constant access mechanisms
Subramaniam Maiyuran, Gold River, CA (US); Sudarshanram Shetty, Portland, OR (US); Travis Schluessler, Berthoud, CO (US); Guei-Yuan Lueh, San Jose, CA (US); PingHang Cheung, Folsom, CA (US); Srividya Karumuri, San Jose, CA (US); Chandra S. Gurram, Folsom, CA (US); Shuai Mu, San Diego, CA (US); and Vikranth Vemulapalli, Folsom, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 26, 2021, as Appl. No. 17/213,874.
Prior Publication US 2022/0308877 A1, Sep. 29, 2022
Int. Cl. G06F 12/08 (2016.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 12/0837 (2016.01)
CPC G06F 9/30047 (2013.01) [G06F 9/3009 (2013.01); G06F 9/3814 (2013.01); G06F 9/3851 (2013.01); G06F 9/3888 (2023.08); G06F 12/0837 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A graphics processing apparatus comprising:
a graphics processor including a number of execution instances to generate requests for constant data; and
a constant cache to store multiple constant types including bindless, stateless constants not bound to a specific storage location and not having a specific state defined, wherein the constant cache has a single level of hierarchy to store the constant data, wherein the constant cache has a banking structure based on the number of execution instances, and wherein the execution instances are to generate requests for the constant data with unified messaging having a single type of data referencing for the multiple constant types.