US 12,333,304 B2
Methods for performing processing-in-memory operations, and related systems
Dmitri Yudanov, Cordova, CA (US); Sean S. Eilert, Penryn, CA (US); Sivagnanam Parthasarathy, Carlsbad, CA (US); Shivasankar Gunasekaran, Folsom, CA (US); and Ameen D. Akel, Rancho Cordova, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Feb. 20, 2024, as Appl. No. 18/582,520.
Application 18/582,520 is a continuation of application No. 16/841,222, filed on Apr. 6, 2020, granted, now 11,934,824.
Claims priority of provisional application 62/896,228, filed on Sep. 5, 2019.
Prior Publication US 2024/0192953 A1, Jun. 13, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/30 (2018.01); G06F 7/544 (2006.01)
CPC G06F 9/3001 (2013.01) [G06F 7/5443 (2013.01); G06F 9/30032 (2013.01); G06F 9/30043 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system, comprising:
logic configured to:
multiply each bit of a number of bits from an array by a first bit of an input vector from a sequencer to generate a first row of bits;
multiply each bit of the number of bits by one or more additional bits of the input vector to generate one or more additional rows of bits; and
generate an output row of bits based on at least the first row of bits and the one or more additional rows of bits.