| CPC G06F 7/4876 (2013.01) [G06F 5/012 (2013.01); G06F 7/5443 (2013.01); G06F 2207/3824 (2013.01)] | 17 Claims |
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1. A processing device, comprising:
multiplier circuitry having a first port configured to receive a signal part covering a mantissa part and an integer part of a first electronic logic signal, a second port configured to receive a mantissa part of a second electronic logic signal, and an output port configured to output an electronic logic signal representing a product of mantissas represented by the mantissa parts of the first and second electronic logic signals in response to a mode signal indicating that the first electronic logic signal represents a floating-point number and output an electronic logic signal representing a product of an integer represented by the integer part and a mantissa represented by the mantissa part of the second electronic logic signal in response to the mode signal indicating that the first electronic logic signal represents an integer;
an aligning circuit having a first port configured to receive an exponent part of a third electronic logic signal, a second port configured to receive an electronic logic signal representing an exponent of a product of the first and second electronic logic signals, and a third port configured to receive a mantissa part of the third electronic logic signal, the aligning circuit being configured to shift a signal applied to the third port of the aligning circuit based on signals applied to the first and second ports of the aligning circuit to generate and output a shifted electronic logic signal to an output port;
an arithmetic logic circuit having a first port which a signal outputted from the output port of the aligning circuit is applied, a second port which a signal outputted from the output port of the multiplier circuitry is applied, and an output port configured to output an electronic logic signal representing a mantissa of a sum of a product of the first and second electronic logic signals and the third electronic logic signal in response to signals applied to the first and second ports of the arithmetic logic circuit; and
a first exponent calculating circuit having a first port configured to receive an exponent part of the first electronic logic signal, a second port configured to receive an exponent part of the second electronic logic signal, and an output port configured to output an electronic logic signal representing an exponent of a product of the first and second electronic logic signals in response to signals applied to the first and second ports of the first exponent calculating circuit,
wherein the electronic logic signal outputted from the output port of the first exponent calculating circuit is generated further in response to the mode signal indicting whether the first electronic logic signal represents a floating-point number or an integer.
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