CPC G06F 30/343 (2020.01) [G06F 30/3308 (2020.01); G06F 11/3457 (2013.01); G06F 30/367 (2020.01)] | 9 Claims |
1. A method for processing simulation data with the simulation to split a digital product design into multiple FPGAs for synchronous simulation, which comprises:
simultaneously collecting the simulation waveform data of said multiple FPGAs and adding a time stamp to the waveform data of each FPGA collected in each collection period, and
storing the waveform data of said multiple FPGAs in the form of a link list according to said time stamp.
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