| CPC G06F 30/33 (2020.01) | 15 Claims |
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1. An integrated circuit for validating logic key, the integrated circuit (IC) comprising:
key input circuit couple to a fuse check circuit, wherein the key input circuit includes at least, a plurality of XOR and XNOR logic gates and the key input circuit is for performing the steps of:
receiving a secret key from a user into the IC;
determining status of one or more antifuse circuit;
validating the secret key;
in responsive to the secret key not matching an original secret key, determining whether an antifuse threshold has been reached;
in responsive to determining that the antifuse threshold has been reached, disabling the IC, wherein disabling the IC based on unsuccessful attempts by an incorrect secret key;
in responsive to the secret key matching the original secret key, enabling the IC; and
in responsive to determining that the antifuse threshold has not been reached, activating the one or more antifuse circuit;
charge pump circuit coupled to the fuse check circuit and a switch matrix, wherein the fuse check circuit is a comparator circuit and the charge pump circuit is a voltage doubler circuit; and
the one or more antifuse circuit connected to the switch matrix.
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