US 12,333,227 B1
Machine-learning-based design-for-test (DFT) recommendation system for improving automatic test pattern generation (ATPG) quality of results (QoR)
Apik A. Zorian, Santa Clara, CA (US); Fadi Maamari, San Jose, CA (US); Suryanarayana Duggirala, San Jose, CA (US); Mahilchi Milir Vaseekar Kumar, San Jose, CA (US); and Basim Mohammed Issa Shanyour, Carbondale, IL (US)
Assigned to SYNOPSYS, INC., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Sunnyvale, CA (US)
Filed on Oct. 18, 2023, as Appl. No. 18/489,341.
Application 18/489,341 is a division of application No. 17/345,819, filed on Jun. 11, 2021, granted, now 11,829,692.
Claims priority of provisional application 63/038,627, filed on Jun. 12, 2020.
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 30/27 (2020.01); G01R 31/3177 (2006.01); G01R 31/3185 (2006.01)
CPC G06F 30/27 (2020.01) [G01R 31/3177 (2013.01); G01R 31/318536 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
extracting a first set of features from a first integrated circuit (IC) design;
predicting, by a trained machine learning (ML) model which executes on a processor, a set of ranked test-case configurations for the first IC design based on the first set of features, wherein each test-case configuration corresponds to a count of scan chain input and output ports and a scan chain length value;
selecting a first test-case configuration from the set of ranked test-case configurations; and
inserting scan chains in the first IC design based on the first test-case configuration to obtain an updated first IC design.