	US 12,333,181 B2
	Source address memory managment
Xiangang Luo, Fremont, CA (US); Jianmin Huang, San Carlos, CA (US); and Xiaolai Zhu, Shanghai (CN)
Assigned to Micron Techology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 8, 2024, as Appl. No. 18/600,269.
Application 18/600,269 is a continuation of application No. 17/555,160, filed on Dec. 17, 2021, granted, now 11,928,356.
Prior Publication US 2024/0211168 A1, Jun. 27, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/00 (2006.01); G06F 3/06 (2006.01)

CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/064 (2013.01)]

20 Claims

1. An apparatus, comprising:

a memory device comprising multiple dies having planes of blocks of memory cells; and

a controller coupled to the memory device and configured to:

select a source block within a plane of a first die for a memory management operation;

select a destination block within a plane of a second die for the memory management operation;

determine that the destination block corresponds to an incomplete superblock;

store an address of the source block within a metadata portion of a block that is within a plane of a die other than the first die; and

perform the memory management operation to transfer data from the source block to the destination block.