US 12,333,165 B2
Configuring command/address channel for memory
Michael Dieter Richter, Ottobrunn (DE); Wolfgang Anton Spirkl, Germering (DE); Thomas Hein, Munich (DE); Peter Mayer, Neubiberg (DE); and Martin Brox, Munich (DE)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 18, 2022, as Appl. No. 17/890,772.
Application 17/890,772 is a continuation of application No. 16/674,987, filed on Nov. 5, 2019, granted, now 11,449,249.
Claims priority of provisional application 62/771,420, filed on Nov. 26, 2018.
Prior Publication US 2022/0391114 A1, Dec. 8, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/24 (2006.01); G06F 3/06 (2006.01); G06F 9/00 (2018.01); G06N 3/045 (2023.01); G06N 3/08 (2023.01)
CPC G06F 3/0632 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0673 (2013.01); G06N 3/045 (2023.01); G06N 3/08 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
configuring, at a first time, a component to use a first quantity of pins and a first quantity of cycles to communicate commands via a channel;
communicating, based at least in part on configuring the component at the first time, a command over the channel in accordance with the first quantity of pins and the first quantity of cycles; and
configuring, at a second time that occurs after the first time and based at least in part on observed information associated with the commands, the component to use a second quantity of pins, a second quantity of cycles, or both, to communicate the commands via the channel, the first quantity of pins being different than the second quantity of pins, the first quantity of cycles being different than the second quantity of cycles, or both.