US 12,333,160 B2
Memory read operation using a voltage pattern based on a read command type
Yu-Chung Lien, San Jose, CA (US); Ching-Huang Lu, Fremont, CA (US); and Zhenming Zhou, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 8, 2024, as Appl. No. 18/629,102.
Application 18/629,102 is a continuation of application No. 17/817,465, filed on Aug. 4, 2022, granted, now 11,972,122.
Prior Publication US 2024/0256155 A1, Aug. 1, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0625 (2013.01) [G06F 3/0653 (2013.01); G06F 3/0673 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
one or more components configured to:
identify a voltage pattern to be used to execute a read command, to read data stored by the memory device, based on a type of the read command,
wherein a first voltage pattern is identified if the type of the read command is a first type and a second voltage pattern is identified if the type of the read command is a second type,
wherein the second voltage pattern is different from the first voltage pattern,
and wherein:
the second voltage pattern consumes less power than the first voltage pattern, or
the second voltage pattern is associated with a longer read time than the first voltage pattern; and
apply the identified voltage pattern to perform a read operation based on the read command,
wherein the first voltage pattern is applied if the type of the read command is the first type and the second voltage pattern is applied if the type of the read command is the second type.