US 12,333,159 B2
Abrupt power loss management
Marco Redaelli, Munich (DE)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Nov. 16, 2023, as Appl. No. 18/511,373.
Claims priority of provisional application 63/479,619, filed on Jan. 12, 2023.
Claims priority of provisional application 63/384,150, filed on Nov. 17, 2022.
Prior Publication US 2024/0168660 A1, May 23, 2024
Int. Cl. G06F 3/06 (2006.01); G06F 1/30 (2006.01)
CPC G06F 3/0625 (2013.01) [G06F 1/30 (2013.01); G06F 3/0619 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A memory device, comprising:
one or more components configured to:
receive a peripheral component interconnect express reset (PERST) signal,
wherein the one or more components, to receive the PERST signal, are configured to identify that the PERST signal has transitioned from a high state to
a low state;
perform a write protect operation based on receiving the PERST signal; and
initiate a reduced power consumption state of the memory device based on a completion of the write protect operation.