US 12,333,158 B2
Efficient memory power control operations
Jean J. Chittilappilly, Maynard, MA (US); Kevin M. Brandl, Austin, TX (US); and Michael L. Choate, Georgetown, TX (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Jun. 29, 2022, as Appl. No. 17/853,393.
Prior Publication US 2024/0004560 A1, Jan. 4, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0625 (2013.01) [G06F 3/0659 (2013.01); G06F 3/0673 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A data processor adapted to couple to a memory, comprising:
a memory operation array comprising a command portion and a data portion;
a power engine having an input for receiving power state change request signals and an output for providing memory operations responsive to instructions stored in said command portion; and
an initialization circuit for populating said data portion with a plurality of mode register values for a predetermined power state for each of a predetermined number of memory devices,
wherein the power engine is configured to:
program a first mode register of a first memory device with a first value in a first location of the memory operation array;
then program the first mode register of at least one other memory device using a corresponding value in one or more corresponding locations of the memory operation array after the first location in a sequence; and
then program a second mode register of the first memory device using a second value in a second location after the one or more corresponding locations of the memory operation array.