US 12,333,153 B2
Memory device and operating method of the memory device
Sung Yong Lim, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Nov. 21, 2022, as Appl. No. 17/991,082.
Claims priority of application No. 10-2022-0083284 (KR), filed on Jul. 6, 2022.
Prior Publication US 2024/0012568 A1, Jan. 11, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0619 (2013.01) [G06F 3/064 (2013.01); G06F 3/0653 (2013.01); G06F 3/0679 (2013.01)] 19 Claims
OG exemplary drawing
 
11. A memory device comprising:
a memory block including selected strings and unselected strings, which are connected between bit lines and a source line;
a source line voltage generator configured to apply a precharge voltage to the source line; and
a select line voltage generator configured to apply one of a positive voltage and a negative voltage to a first select line adjacent to the bit lines and a second select line adjacent to the source line, wherein the first select line and the second select line are connected to the selected strings and the unselected strings,
wherein the select line voltage generator is configured to:
apply the positive voltage to the second select line to precharge the unselected strings when a target voltage of memory cells of selected memory cells included in the selected strings is equal to or lower than a reference voltage; and
apply the negative voltage to the second select line to precharge the unselected strings when the target voltage is higher than the reference voltage.