US 12,333,148 B2
Semiconductor memory devices that perform burst operations
Jinhoon Jang, Suwon-si (KR); and Kyungryun Kim, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Oct. 6, 2022, as Appl. No. 17/938,651.
Claims priority of application No. 10-2021-0140424 (KR), filed on Oct. 20, 2021; and application No. 10-2022-0040041 (KR), filed on Mar. 31, 2022.
Prior Publication US 2023/0124660 A1, Apr. 20, 2023
Int. Cl. G11C 8/00 (2006.01); G06F 3/06 (2006.01)
CPC G06F 3/0613 (2013.01) [G06F 3/0659 (2013.01); G06F 3/0673 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a memory cell array;
a plurality of data input/output (I/O) pins configured to receive write data to be stored in the memory cell array or to output read data stored in the memory cell array; and
a clock divider configured to generate a second command clock signal based on a first command clock signal,
wherein:
the semiconductor memory device is configured to perform a burst operation in which a single data set comprising a plurality of data bits is input or output through the plurality of data I/O pins based on a single command received from an external memory controller,
a number of the plurality of data I/O pins corresponds to an integer that is not a power-of-two,
a burst length representing a unit of the burst operation corresponds to an integer that is not a power-of-two,
the memory cell array and the plurality of data I/O pins are configured to operate based on the second command clock signal and a data clock signal, and
a period of the second command clock signal divided by a period of the data clock signal corresponds to an integer that is not a power-of-two.