US 12,333,142 B2
Data processing method for memory device, apparatus, and system
Xiaoming Zhu, Shanghai (CN); and Yigang Zhou, Shanghai (CN)
Assigned to HUAWEI TECHNOLOGIES CO., LTD., Shenzhen (CN)
Filed by Huawei Technologies Co., Ltd., Shenzhen (CN)
Filed on Aug. 26, 2022, as Appl. No. 17/896,884.
Application 17/896,884 is a continuation of application No. PCT/CN2021/071134, filed on Jan. 11, 2021.
Claims priority of application No. 202010124905.5 (CN), filed on Feb. 27, 2020; and application No. 202010740899.6 (CN), filed on Jul. 28, 2020.
Prior Publication US 2022/0404973 A1, Dec. 22, 2022
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0607 (2013.01) [G06F 3/0659 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A data processing method for a memory device, wherein the memory device comprises a controller, a first memory, and a second memory, wherein the controller separately communicates with a processor, the first memory, and the second memory, wherein read/write performance of the first memory is higher than read/write performance of the second memory, and wherein the method comprises:
receiving an operation request of the processor, wherein the operation request comprises a logical address; and
accessing a first one of the first memory or the second memory based on the logical address, wherein accessing the first one of the first memory or the second memory comprises:
performing, in response to the operation request being a read request:
writing, in response to the controller determining that the first memory does not have a read hit, data that is in the second memory into the first memory at a physical address in the first memory associated with the logical address; and
reading to-be-read data from the first memory according to the logical address; and
performing, in response to the operation request being a write request:
writing to-be-written data to the first memory according to the logical address; and
marking, in response to second data corresponding to the logical address existing in the second memory, the second data as invalid data.