US 12,333,141 B2
Memory system and method of controlling non-volatile memory
Shizuka Sekigawa, Tokyo (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on May 15, 2024, as Appl. No. 18/664,553.
Application 18/664,553 is a continuation of application No. 17/685,952, filed on Mar. 3, 2022, granted, now 12,019,868.
Claims priority of application No. 2021-129985 (JP), filed on Aug. 6, 2021.
Prior Publication US 2024/0302959 A1, Sep. 12, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0604 (2013.01) [G06F 3/0655 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory system comprising:
a non-volatile memory including at least one memory chip;
a controller electrically coupled to the non-volatile memory, and configured to:
transmit a first instruction to the non-volatile memory;
transmit a second instruction to the non-volatile memory after transmitting the first instruction;
determine whether the non-volatile memory includes an interface chip; and
in response to determining that the non-volatile memory includes the interface chip, the second instruction is transmitted to the non-volatile memory after a first period following transmission of the first instruction elapses,
in response to determining that the non-volatile memory does not include the interface chip, the second instruction is transmitted to the non-volatile memory after a second period following transmission of the first instruction elapses, and
the first period is different from the second period.