| CPC G06F 3/0604 (2013.01) [G06F 3/0631 (2013.01); G06F 3/0634 (2013.01); G06F 3/0679 (2013.01)] | 18 Claims |
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1. A memory system connectable to a host, the system comprising:
a first memory including a nonvolatile memory cell array;
a second memory configured to operate at higher speed than the first memory; and
a memory controller configured to:
in response to a write command from the host, with respect to first data instructed to be written by the write command,
execute a first operation that is data transfer from the host to the second memory;
execute a second operation that is data transfer from the second memory to the first memory; and
cause the first memory to execute a third operation of writing data transferred by the second operation to the memory cell array, wherein the memory controller is further configured to:
execute switching between a first mode and a second mode in response to an access pattern from the host; and
in response to a read command from the host to read the first data,
in the first mode:
before a first timing that is a timing at which the second operation for the first data is started, transfer, from the second memory to the host, second data that is the first data stored in the second memory by the first operation, and after the first timing, acquire, from the first memory, third data that is the first data written to the memory cell array by the third operation, and transfer the third data to the host; and
in the second mode:
before a second timing that is a timing at which the second operation for the first data is completed, transfer the second data from the second memory to the host, and
after a third timing that is a timing at which the third operation for the first data is started, acquire the third data from the first memory and transfer the third data to the host.
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