| CPC G06F 21/577 (2013.01) [G06F 21/554 (2013.01); G11C 8/18 (2013.01); G11C 11/4078 (2013.01); G11C 29/022 (2013.01); G11C 29/50004 (2013.01); G11C 29/52 (2013.01); G06F 2221/034 (2013.01); G11C 2029/5002 (2013.01)] | 20 Claims |

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1. A memory device comprising:
at least one memory including a plurality of memory cells disposed in rows and columns; and
a controller, communicatively coupled to the at least one memory;
wherein the controller maintains data integrity in the at least one memory by executing operations comprising:
receiving a row activation (ACT) command for a row;
starting a RAS counter and incrementing the RAS counter in a subsequent instance of an edge of a clock;
determining if a pre-charge (PRE) command has been received for the row, and if said pre-charge command has been received, setting the RAS counter to zero;
determining whether the RAS counter is greater than a RAS clobber counter threshold (RCCT) if said pre-charge command was not received;
triggering another row activation command for a second row (ACT+1) and setting the RAS counter to zero; and
incrementing the RAS counter at another edge of the clock when the RAS counter is greater than the RCCT.
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